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Slide 1: Chapter 6 PCB Layout Considerations
Slide 2: Power & Ground Planes 1.A low impedance path for power from its source to the components on the PCB . 2.A physical channel to vent and move heat from the components. 3.Electrostatic shielding between the electromagnetic fields of signal traces that run on both sides of the planes. 4.A sheet capacitance for the ground plane that exist on other layers of the PCB . This in turn provides additional AC bypass within the power circuitry of the PCB.
Slide 3: The capacitance of the planes can be calculated by the following equations: C=0.0885ER[(N-1)*A]/t Where ER = The Relative Dielectric Constant N = Number of Plates A = Area of one side of one Plate in square centimenters t = Thickness(separation of plates) in centomeers C = 0.225 ER[(N-1)*A`]/t` Where ER = The Relative Dielectric Constant N = Number of Plates A` = Area of one side of one Plate in square centimenters t ` = Thickness(separation of plates) in centomeers
Slide 4: For example, using a 10-inch by 10-inch FR-4 board with an ER of 4.1 and a 0.005-inch separation between the power and ground plane , the capacitance is calculated as: C = 0.225(4.1)[(2-1)*100]/0.005 = 18,450 pF
Slide 5: Ground Island
Slide 7: Vias Vias are commonly used to connect the power plane to the power traces that ultimately attach to the power pins of the components.
Slide 8: Power Traces
Slide 9: Signal Return Paths
Slide 10: Signals The second area with which we need to be concerned is the routing of clock signals. The goal,obviously,is to provide a pathway for the clock that has no noise,has uniform impedance,and does not produce any EMI. The next section discusses the affects board layout has on these attributes.
Slide 11: Crosstalk
Slide 12: To illustrate the effects of spacing , the mutual inductance LM can be calculated with the following equation: LM = L/(1+(s/h)2) Where : L = Inductance if the Wire s = separation between the wires h = height above the plane
Slide 13: The mutual capacitance CM injects current IM into the victim trace and can be calculated as : IM = CM d Vs/dt Where : Vs is the source voltage.
Slide 15: To minimize the effects of magnetic field coupling,three basic rules should be followed. 1.First , separate the traces with more distance. 2.The second method of decreasing the coupling is to shield the target trace. 3.A third way to reduce the impact of crosstalk is to use differential signaling.
Slide 16: Guard Traces
Slide 17: Layers In order to keep noise at a minimum and to achieve the best in signal integrity,control of the PCB layers is required.
Slide 18: Vias in Traces 1.Make vias as large as possible ( more area equals less inductance and resistance ). 2.Plate external layers with the maximum thickness of copper during fabrication. 3.Plating or filling the via holes solid.
Slide 19: EMI Generation PCB traces act as small antennas to the clock signals on the traces. In practical terms, the goal is to provide a `poor` antenna to prevent unwanted EMI.
Slide 20: Differential Clock Traces 1.The traces ( true and complement ) must be physically equal in length. 2.Trace the signals alike. 3.Keep the traces constantly spaced. 4.Keep the two traces ( true and complement ) close to each other
Slide 21: Conclusion PCB layout is an important aspect of design especially when implementing high-speed digital clocks. It is important to remember that traces,vias,and planes have different characteristics when highspeed speed signals are present.