Slide 1: Low Noise Amplifier Design for the 1900MHz Application Sean kim (hskim@ansoft.co.kr) Application Engineer Ansoft Korea 1
Slide 2: introduction  This presentation was developed for Samsung Electronics train center. They want to Step –by step serenade training material with practical circuit (for the Handset ) : total page is 72. This low noise amplifier design procedure was optimized to increase amplifier linearity.( e.g IP3 point , IMD, P1 dB ) Selected device is SiGe NPN TR BFP620 which was not included for ADS 1.5 Device Library.   2
Slide 3: Agenda   Overall Requirements Amplifier Design Using Harmonica       Low noise amplifier design procedure Device selection Improvement IP3 & Stability (Series negative feedback using inductor) Matching Circuit Design using the Smith Tool PCB Layout generation. Simulation & measured data comparison. 3
Slide 4: Overall Requirement Design goal of Low Noise Amplifier Frequency Range Gain(dB) NF(dB) P1 (dBm) OIP3(dBm) Return loss Bias (Vce, Ic) Component No.  1900Mhz 14dB  1dB 4dBm 23dBm <10dB Low power (2V, 8mA) ~ 12 component Design Consideration of Low noise Amplifier using Non-linear model. : the order of priority => Must be trade off other conditions 1. Linearity (IMD3, IP3, G1 dB)& DC. Bias consumption (Vce, Ic,) 2. Stability (K, B1) 3. Noise figure(NF,Fmin) 4. Standing wave ratio (VSWR, S11,S22) 4
Slide 5: Low noise amplifier design  Low noise amplifier design procedure              Device selection. Package element included nonlinear model construction. Bias circuit decision. Nonlinear Harmonic balance simulation.(P1 dB,IP3) Improvement Stability K & IP3 using inductor. S-parameter extraction Power Gain circle & Noise figure matching using Smith tool Input Output matching circuit generation Low frequency stability increase Lumped inductor to microstrip line inductor Printed Circuit Board layout using S2A Small signal analysis & Input Output VSWR, K, B1 Nonlinear analysis [Transduce Gain, G1dB, IMD3, IP3, ACPR, Spurious Emission analysis]  Compare to Measured data. 5
Slide 6:  Device selection  Low noise amplifier design Using Siemens(infineon) SiGe bipolar TR BFP620 6
Slide 7: Low noise amplifier design  Improvement IP3    D.C bias consumption was declined that a decrease of ½ (40mw -> 16mW) Consist negative feed back circuit using serial inductor degeneration.( Gain decrease, IP3 increase) Two Inductor add on each lead frame. Turning Inductor 7
Slide 8: Low noise amplifier design  Improvement Stability K (small signal analysis)  L value of 1.5 nH as changing the inductor value until K value becomes 1.(up to K=1) L value is 1.5nH, K=1, B1>0 (Unconditional stability) Turn the inductor value.(L value is 1.5nH, IP3 : ~ 23dBm.)   K=1 IP3 8
Slide 9: Low noise amplifier design  Improvement IP3, decrease Gain simulation  Gain decrease 4.5dB and IP3 increase 4 dBm, when added 1.5nH inductor. VCE=2V, 20mA VCE=2V, 8mA IP3 Emitter inductor added. GAIN 9
Slide 10: Low noise amplifier design   Matching circuit design using Smth tools. bias circuit and matching circuit is same topology used.  Serial capacitor and parallel inductor is match network. It also provides a convenient form of DC bias feed-through for the device. Power gain circle and noise figure circle is used for the good input VSWR.  KCS GPCL GPCS 15 14.5 14.8 KCL Power Gain (s-plan) circle and NF circle cross point 10
Slide 11: Low noise amplifier design  Translate Lumped to Microstrip for PCB board Layout. Input ,Output matching circuit added Bypass Capacitor(0.1uF) is added for the improvement IMD.   Input matching Output matching 11
Slide 12: Low noise amplifier design    Printed Circuit Board layout using S2A Via is fenced around circuit using S2A. D.C noise bypass Capacitor(10uF) was added. Filled screen  Unfilled screen 12
Slide 13: Low noise amplifier design  Serenade layout data was transformed to PADS Power PCB ascii file format Using to S2A. 13
Slide 14: Low noise amplifier design  Fabricated Low noise Amplifier PCB board. 1Cm 1Cm 14
Slide 15: Low noise amplifier design  Compare simulation and measured data. Fc=(1950MHz)   S21:14.6(serenade) S11:-27 (serenade) 14.16 dB(measured), S12:-17.4(serenade) -25.4dB (measured), ,S22:-11 (serenade) -19.17dB(measured) -7.9dB (measured) (serenade) (serenade) (measured) (serenade) (serenade) (serenade) (measured) (measured) S21 S11 S22 S12 Diff. (measured) 15
Slide 16: Low noise amplifier design  Compare simulation and measured data. (Wide range)   NF value is measured 1.1~ 1.2 dB. (0.3 dB increase) => It cause for Q value input matching circuit L, C. IMD3 is measured 51dBc when each tone ouput is 0dBm ,So IP3 is 25.5dBm. ( OIP3 = output power(each tone) +1/2* (IMD3) ) (serenade) (measured) S21 S11 S22 S12 16
Slide 17: Low noise amplifier design   Summary 1. Serenade was used to model the performance of a 1950 MHz DCS band Low noise amplifier. 2. RF single-tone, RF two-tone and digital modulation simulation data were presented. 3. A comparison between simulated and measured performance characteristics of the LNA to be in good agreement.    reference Gerard Wevers, Infineon Technologies, “A High IIP3 Low Noise Amplifier for 1900 MHz Applications Using the SiGe BFP620 Transistor”  17