Slide 1: TTL/LS vs. CMOS
Reliability & Neutron Radiation.
Slide 2: What’s really going on
This study has taken two common types of semiconductors and tested to see which is more reliable after exposure to neutron radiation.
Slide 3: TTL/LS explained
Transistor Transistor Logic / Low-Power Schottky. These chips have gates constructed of bipolar transistors using low internal voltages. Uses 80% less power than TTL.
Slide 4: CMOS explained
Complementary Metal Oxide Semiconductor. Uses metal oxide semiconductor field effect transistors (MOSFETs) instead of bipolar transistors. Highest number of transistors per unit area.
Slide 5: Irradiation procedure
The chips were irradiated using the U.M.R. nuclear reactor. The gate's accuracy was determined and logged using a system of my own design. Next, The chips were irradiated again for a set interval of time, tested, and repeated until the chips failed.
Slide 6: How are they irradiated?
First the chips are sealed in vials. Next the vials are loaded into the BRT (Bare Rabbit Tube.) The reactor operator then activates the BRT sending the vial down into the core. This time from the surface to the core is under .5 sec. The chips stay down by the core for a set time and then are automatically pulled back up after the time has elapsed. The chips are then put into storage until testing.
Slide 7:
The “Rabbit Cage” is where vials are loaded into the BRT. Uses a slight vacuum to keep radioactive dust, etc from escaping. Constantly monitored so that if a specimen is “too hot” it can be sent back into the pool to “cool off.”
The “Rabbit Cage”
Slide 8:
These pipes carry the vials into the core. The BRT uses nitrogen gas to propel the vials. This tube is unshielded. The other is the “Cad Rabbit,” It is used to allow only “slow neutrons” through.
The BRT
Slide 9: And the Core
The Core is at the very bottom of the pool. The Core configuration is Red = fuel, Green = control rods, and the white rabbit is where the chips were.
Slide 10: Testing the Chips
Using a microcontroller called the Basic
Stamp 2, running a program written by myself, to test the chips accuracy by testing each gate hundreds of times.
Slide 11: Testing by the Numbers
The program can run tests a maximum of 65,000 times per gate per input type per chip. • 4 gates per chip. • 4 input types per gate. 65,000 x 4 x 4 = 1,040,000 tests per chip.
Slide 12: The Results
The graph shows the total number of gates that failed in each group and the exposure that the gates had when they failed. No TTL/LS gates failed, however the CMOS gates became very unreliable. Twenty gates were tested per group with four groups.
Slide 13: And the Conclusion is ...
TTL/LS is better hardened against radiation than CMOS.
Slide 14: Special Thanks to…
Dr. Akira Tokuhiro, UMR reactor director; for allowing me to do this project and for introducing me to the Nuclear Engineering Department Mr. Kurt Koch, UMR Physics Student; his time and patients in explaining to me what could and could not be done at the reactor, allowing me to use his computer account, and for allowing me to use the Society of Physics Students room at the Physics building. Brian Porter, UMR reactor electronics specialist; for supervising me while I was at the reactor. William Bonzer, UMR reactor manager; for allowing me the necessary time at the UMR reactor UMR Society of Physics Students; for using their facilities during my summer stay at UMR Mrs. Connie Henry; my Science Research and College Chemistry instructor. My Parents for their patience and support.
Slide 15: The End
Thank you very much:
Kevin Johnson West Plains Missouri
2002 Rolla ISEF
